The present invention relates generally to semiconductor manufacturing, and more particularly to a method for manufacturing a component overlying a semiconductor substrate.
Passive components such as capacitors and inductors are often coupled to semiconductor devices externally as discrete components. However, external coupling can be complicated in that it requires consideration of parasitic effects of the passive-active device interface. It additionally incurs costs both in terms of the individual discrete components and by decreasing the effective surface area of the semiconductor device in order to accommodate the interface. Reliability issues can also be a concern due to integration complexities associated with externally mounting the passive components to the semiconductor device. In response to these issues, passive components are more commonly being integrated into the backend of semiconductor manufacturing processes and the components formed as part of the semiconductor device, for example overlying the semiconductor device passivation layer.
Shown in FIG. 1 is a top down view of an inductor 10, and shown in FIG. 2 is a cross-sectional view of a portion of the inductor 10 that includes lead portions 12, 14, and 16 formed over a passivation layer 5 and interconnect 3 of a semiconductor device 1. A blanket adhesion/barrier layer 7 and a seed layer 9 have been physically vapor deposited (PVD) overlying the passivation layer 5 and interconnect 3, and the lead portions 12, 14, and 16 have been deposited over the seed layer 9. The lead portions have been formed using conventional patterning and plating processes.
To complete fabrication of the inductor 10, portions of the exposed seed layer 9 and adhesion/barrier layer 7 must be removed to electrically isolate the leads 12, 14, and 16. Preferably, processes used to remove the exposed portions of the seed layer 9 and adhesion/barrier layer 7 are capable of selectively removing them without removing too much bulk material from the leads 12, 14 and 16. Ideally, the processes used to remove the seed layer 9 and barrier layer 7 should not attack the leads 12, 14, and 16. One etchant reported to selectively etch PVD copper with respect to electroplated copper is disclosed in U.S. Pat. No. 5,409,567 (hereinafter the ""567 patent), which is assigned to the assignee hereof, and is hereby incorporated by reference. However, the etchant disclosed in the ""567 patent is affected by changes in pH and requires the addition of a buffer for stability. In addition, its effectiveness at removing the seed layer is impacted by spacing dimensions between the leads 12, 14, and 16. Other etchants, such as a solution of sodium chlorite and ammonium hydroxide, which have also been used, are too aggressive and remove too much of the bulk material from the electric leads 12, 14 and 16 while removing the seed layer 9.
For example, referring to FIG. 3, when the spacing dimension is reduced below a minimum critical dimension 24, the ability of the solution to etch the seed and barrier layer becomes impaired and residual portions 34 of the seed and barrier layer cannot be removed. Failure to remove residual portions 34 results in electrical shorts between the leads 14 and 16, which can result in failure or reliability problems. In addition, areas exposed by dimensions greater than the critical dimension, such as for example, dimension 22, may have non-planar or stepped surfaces. In these areas, residual conductive material 32 may become trapped and create paths for electrical shorts to occur in other regions of the passivation layer.
One possible solution to these problems includes increasing the overetch time or using more aggressive etchants. However, as shown in FIG. 4, this can have the effect of etching too much of the bulk conductive material that forms the conductive leads 12, 14, and 16. This can result in excessive thinning of the leads, which can alter the component""s characteristics or impact its functionality. In extreme cases, too much overetch can result in peeling of the leads 12, 14, or 16. This, coupled with the inherent non-uniformity of wet processing, can result in component peeling in some areas of the semiconductor substrate before removing the seed layer from other parts of the wafer. The effect and impact of non-uniformity becomes more pronounced when simultaneously etching multiple wafers.